-
On
cmos power( formula- P=CV*Vf
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Lowest
noise margin in which logic family--
a) TTL b) CMOS c)
biCMOS d) all have
same
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If
CMOS has tr(rise time)=tf.find Wp/Wn. given beta(n)=2*beta(p)
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gm
of a transistor is proportional to
a)Ic b)Vt c)1/Vt d)none
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If
A and B are given in 2's complement find A-B in
decimal.
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Set
up time,hold time ,clock to Q delay time (very
important)
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.3
questions on opamp (transfer function)(2 marks each)
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2
questions on sequence detector (2 marks each)
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Logic
function boolean expressions(true/false) (3
question-1 mark each)probabily all false
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In
I/O mapped how do you represent memory(1 mark)
-
The
design of FSM(finite state machine) will--
a) increase time of design
b) increase delay
c) increase power
d) all of the above
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K-map
minimization
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Phase
locked loop(PLL) 1 question sachin